mccormick.northwestern.edu

VLSI Lab Wins ISLPED Design Contest Award

Professor Jie Gu and members of his Very Large-Scale Integration Lab team won the Design Contest Award at the premier ACM/IEEE International Symposium on Low Power Electronics and Design Northwestern ...
Nature

Gate Sizing and Power Optimization in VLSI Design

Gate sizing is a fundamental technique in VLSI design, where the dimensions of transistors and gates are carefully adjusted to achieve optimal performance, minimise power consumption and reduce delay.
mccormick.northwestern.edu

VLSI Lab Presents Three Papers at the ‘Chip Olympics’

Professor Jie Gu and members of his Very Large-Scale Integration Lab team presented three papers and a live demonstration on brain-machine-interface at the premier 2024 IEEE International Solid-State ...
Semiconductor Engineering

Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design

“With the improvement of VLSI technology, on-chip power grid design is becoming more challenging than before. In this design phase of VLSI CAD, power grids are generated in order to make power and ...